Wireless Transceivers

Companding Filters

[1] On the exact realization of LOG-domain elliptic filters using the signal flow graph approach,Psychalinos; C.; Vlassis, S.; Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on]Volume 49, Issue 12, Dec. 2002 Page(s):770 - 774

[2] A systematic design procedure for square-root-domain circuits based on the signal flow graph approach,Psychalinos, C.; Vlassis, S.; Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on [see also Circuits and Systems I: Regular Papers, IEEE Transactions on] Volume 49, Issue 12, Dec. 2002 Page(s):1702 - 1712

[3] On the exact realization of log-domain elliptic filters using the signal flow graph approachPsychalinos, C.; Vlassis, S.; Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on]Volume 50, Issue 6, June 2003 Page(s):325 - 325

[4] A systematic design procedure for square-root-domain circuits based on signal flow graph approach,Psychalinos, C.; Vlassis, S.; Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on [see also Circuits and Systems I: Regular Papers, IEEE Transactions on]Volume 50, Issue 5, May 2003 Page(s):728 - 728

[5] A square-root domain differentiator,Vlassis, S.; Psychalinos, C.;Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium onVolume 2, 26-29 May 2002 Page(s):II-217 - II-220 vol.2

[6] A signal flow graph based design method for square-root domain circuits,Psychalinos, C.; Vlassis, S.; Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on Volume 2, 26-29 May 2002 Page(s):II-209 - II-212 vol.2

[7] A High Performance Square-Root Domain Integrator; Costas Psychalinos and Spiridon Vlassis; Analog Integrated Circuits and Signal Processing, Volume 32, Number 1 / July, 2002, Pages 97-101

[8] A Novel Log-Domain Differentiator; Spiridon Vlassis and Costas Psychalinos; Analog Integrated Circuits and Signal Processing, Volume 32, Number 3 / September, 2002, Pages 285-287

[9] A Square-Root Domain Differentiator Circuit; Spiridon Vlassis and Costas Psychalinos; Analog Integrated Circuits and Signal Processing, Volume 40, Number 1 / July, 2004 Pages 53-59

Analogue computational circuit design

[1] Current-mode non-linear building blocks based on floating-gate transistors;Vlassis, S.; Siskos, S.; Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on Volume 2, 28-31 May 2000 Page(s):521 - 524 vol.2

[2] Analogue squarer and multiplier based on floating-gate MOS transistors;Vlassis, S.; Siskos, S.; Electronics Letters; Volume 34, Issue 9, 30 April 1998 Page(s):825 - 826

[3] Design of voltage-mode and current-mode computational circuits using floating-gate MOS transistors;Vlassis, S.; Siskos, S.; Circuits and Systems I: Regular Papers, IEEE Transactions on [see also Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on] Volume 51, Issue 2, Feb 2004 Page(s):329 - 341

[4] CMOS current-mode pseudo-exponential function circuit;Vlassis, S.;Electronics Letters; Volume 37, Issue 8, 12 Apr 2001 Page(s):471 - 472

[5] Analog CMOS four-quadrant multiplier and divider;Vlassis, S.; Siskos, S.; Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on Volume 5, 30 May-2 June 1999 Page(s):383 - 386 vol.5

[6] Analogue computational circuits based on floating-gate transistors;Vlassis, S.; Yiamalis, Th.; Siskos, S.; Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on Volume 1, 5-8 Sept. 1999 Page(s):129 - 132 vol.1

[7] Differential-voltage attenuator based on floating-gate MOS transistors and its applications;Vlassis, S.; Siskos, S.; Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on [see also Circuits and Systems I: Regular Papers, IEEE Transactions on] Volume 48, Issue 11, Nov. 2001 Page(s):1372 - 1378

[8] Low-voltage CMOS VT extractor; Vlassis, S.; Psychalinos, C. Electronics Letters;Volume 43, Issue 17,16 Aug 2007 Page(s) 921-923

Piezoresistive interfacing circuits

[1] A piezoresistive pressure sensor interfacing circuit;Vlassis, S.; Siskos, S.; Laopoulos, T.;Instrumentation and Measurement Technology Conference, 1999. IMTC/99. Proceedings of the 16th IEEE;Volume 1, 24-26 May 1999 Page(s):303 - 308 vol.1

[2] An interface circuit for piezoresistive pressure sensors;Vlassis, S.; Siskos, S.;Electrotechnical Conference, 1998. MELECON 98., 9th Mediterranean;Volume 1, 18-20 May 1998 Page(s):469 - 473 vol.1

[3] Pressure sensors interfacing circuit with digital output;Vlassis, S.; Laopoulos, Th.; Siskos, S.; Circuits, Devices and Systems, IEE Proceedings-Volume 145, Issue 5, Oct. 1998 Page(s):332 - 336

[4] A Signal Conditioning Circuit for Piezoresistive Pressure Sensors With Variable Pulse-Rate Output; S. Vlassis and S. Siskos; Analog Integrated Circuits and Signal Processing, Volume 23, Number 2 / May, 2000 Pages 153-162

[5] An interfacing circuit for piezoresistive pressure sensors with frequency output; S. Vlassis; S. Siskos; International Journal of Electronics, Volume 87, Issue 1 January 2000 , pages 119 - 127

Analog Implementation of non linear filter for image processing

[1] Analog implementation of fast min/max filtering;Siskos, S.; Vlassis, S.; Pitas, I.; Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on]
Volume 45, Issue 7, July 1998 Page(s):913 - 918

[2] Analog implementation of an order-statistics filter;Siskos, S.; Vlassis, S.; Pitas, I.; Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on [see also Circuits and Systems I: Regular Papers, IEEE Transactions on]
Volume 46, Issue 10, Oct. 1999 Page(s):1296 - 1300

[3] CMOS outlier rejection circuit;Vlassis, S.; Siskos, S.;Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on [see also Circuits and Systems I: Regular Papers, IEEE Transactions on];Volume 48, Issue 7, July 2001 Page(s):910 - 914

[4] Analog implementation of an order statistics filter;Vlassis, S.; Siskos, S.; Pitas, I.; Electrotechnical Conference, 1998. MELECON 98., 9th Mediterranean; Volume 1, 18-20 May 1998 Page(s):649 - 653 vol.1

[5] Analog CMOS design of the incremental credit assignment (ICRA) scheme for time series classification; Vlassis, S.; Siskos, S.; Hatzopoulos, A.; Petridis, V.; Kehagias, A.; Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Volume 2, 31 May-3 June 1998 Page(s):324 - 327 vol.2

[6] Current-mode analogue median filter;Vlassis, S.; Siskos, S.; Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on Volume 3, 5-8 Sept. 1999 Page(s):1353 - 1356 vol.3

[7] High speed and high resolution WTA circuit;Vlassis, S.; Siskos, S.; Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on Volume 2, 30 May-2 June 1999 Page(s):224 - 227 vol.2

[8] CMOS outlier rejection circuit;Vlassis, S.; Siskos, S.;Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on Volume 5, 28-31 May 2000 Page(s):729 - 732 vol.5

[9] A floating gate CMOS Euclidean distance calculator and its application to hand-written digit recognition;Vlassis, S.; Fikos, G.; Siskos, S.; Image Processing, 2001. Proceedings. 2001 International Conference on Volume 3, 7-10 Oct. 2001 Page(s):350 - 353 vol.3

[10] High-speed, accurate analogue CMOS rank filter;Fikos, G.; Vlassis, S.; Siskos, S.; Electronics Letters; Volume 36, Issue 7, 30 March 2000 Page(s):593 - 594

[11] CMOS analogue median circuit;Vlassis, S.; Siskos, S.; Electronics Letters Volume 35, Issue 13, 24 June 1999 Page(s):1038 - 1040

[12] Precision Multi-Input Current Comparator and Its Application to Analog Median Filter Implementation; S. Vlassis and S. Siskos; Analog Integrated Circuits and Signal Processing, Volume 34, Number 3 / March, 2003 Pages 233-245